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[ ak570 1 ] ms0404 - j - 04 2015/10 - 1 - ? ak5701 ??`??`?C?_k??R 16bit a/d `? ak5701 ? ? alc(auto level control) i??????????` ?m?i pll ??`??????? dsp ??A ?? ak5701 24pin qfn ??`????C??m? L 1. ? hC ?? ? ??? ????i ? ????? i digital alc (automatic level control) i ? ? ?? ? ? ? ? ? ? ?`?` `????`?`?? 2s compliment - dsp mode, 16bit ?? 2 s 7. ? ? ???` ? ??R ? dvdd: 1.6 ? M ? ? ? ? ? ? ??` pll & mic - amp i 16 - bit ? ? stereo adc ak5701
[ ak570 1 ] ms0404 - j - 04 2015/10 - 2 - ?? figure 1 . ?? lin1 vcom avdd avss rin1 vcoc mcki sdto bclk lrck dvdd adc mix audio i/f controller pll pdn s e l mcko exlrck exbclk exsdti control register csn cclk cdti s e l lin2 rin2 alc or ivol mpwr dvss csp hpf
[ ak570 1 ] ms0404 - j - 04 2015/10 - 3 - `?? ak5701v n ? 30 ? +85 ? c 24 - pin qfn (0.5mm pitch) ak5701kn ? 40 ? +85 ? c 24 - pin qfn (0.5mm pitch) akd5701 ak5701 u?` ? ak5355vn ?^ ? ak5355vn ak5701 ? ? +15db/0db +30db/+15db/0db ? ? alc ? ?` ? `? i/f ?`?? left justified, i 2 s dsp mode, left justified, i 2 s pll ? ?` ? ?` ? ???` ? ??R 2.1 ? 3.6v avdd=2.4 ? 3.6v dvdd=1.6 ? 3.6v ??` 20 - pin qfn (4.2mm x 4.2mm) 24 - pin q fn (4mm x 4mm) h? ? 40 ? +85 ? c ak5701vn : ? 30 ? +85 ? c ak5701kn : ? 40 ? +85 ? c mpwr rin2 lin2 rin1 lin1 vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck ak5701 top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 2 3 4 5 6
[ ak570 1 ] ms0404 - j - 04 2015/10 - 4 - ???C no. pin name i/o function 1 vcom o ?R? ?R? ???? ???? ??? ???? `????? ???? `???`? ????OO? ??? ?`???`? ?? ?? ?`????? ???? ?`?`? ?`??? ??? ????? ?``?? ?`? ?`??????`?? ??o? ?? ? ???? ?? ? ? ??? ?? ? ? ??? ? ? ???? `???? ?g????????`?A ??? ( lin1, rin1, lin2, rin2) ?????`?????? ? ?????I?? ?????O m?I? ? O ? ? `? `? ??A
[ ak570 1 ] ms0404 - j - 04 2015/10 - 5 - ~?? (avss , dvss= 0v ; note 2 ) paramete r symbol m in . m ax . unit power supplies: analog avdd ? ? C ? ? vina ? ? ? ? ? ? ? ? ?R???????? note 3 . avss dvss ??????A note 4 . lin1/lin+, rin1/lin ? , lin2/rin ? , rin2/rin+ pins note 5 . pdn, csn, cclk, cdti, csp, mcki, exsdti, exlrck, exbclk pins ? : ???????????????^ ? ?X ( avss, dvss=0v ; note 2 ) parameter symbol m in . t yp . max . unit power supplies analog avdd 2.4 3.0 3.6 v ( note 6 ) digital dvdd 1.6 3.0 avdd v note 2 . ?R???????? note 6 . avdd, dvdd ??`????]??? avdd off ? dvdd `??? dvdd off ? avdd off ? ? : ?``??d???v???????? ?
[ ak570 1 ] ms0404 - j - 04 2015/10 - 6 - ?? ( ta=25 ? c ; avdd, dvdd = 3.0v ; a vss=dvss=0v; pll master mode; mcki=12mhz, fs=4 4.0995k hz , bclk=64fs; signal frequency =1khz ; 16bit data; measurement frequency=2 0hz ? 20khz; unless otherwise specified) parameter m in . t yp . max . unit mic amplifier: lin1, rin1, lin2, rin2 pins; mdif1 = mdif2 bits = ? ? mic amplifier: lin+, lin ? ? mic power supply: mpwr pin output voltage ( note 8 ) 2.02 2.25 2.48 v load resistance 0.5 - - k ? adc analog input characteristics: lin1/rin1/lin2/rin2 pins (single - ended inputs) ? ? ? ? power supplies: power supply current: avdd+dvdd power up (pdn pin = ? ???? ???? ac ?????????` ??A mgain1 - 0 bits = 00 ??y?? lin+, lin ? , rin+, rin ? pin ?R?? avdd ?? vin = |(l/rin+) ? (l/rin ? )| = 0.123 x avdd (max)@mgain1 - 0 bits = 01 , 0.022 x avdd (max)@mgain1 - 0 bits = 10 . ?R??? ? adc ??^?? note 8 . ?R avdd ?? vout = 0.75 x avdd (typ) note 9 . ?R avdd ?? vin = 0.107 x avdd (typ)@mgain1 - 0 bits = 01 (+15db), vin = 0.6 x avdd(typ)@mgain1 - 0 bits = 00 (0db) note 10 . 78db(typ)@mgain=0db, 72db(typ)@mgain=+30db note 11 . 89db(typ)@mgain=0db, 77db(typ)@mgain=+30db note 12 . 100db(typ)@mgain=0db, 80db(typ)@mgain=+30db note 13 . pll master mode (mcki=12mhz) ? pmadl = pmadr = pmvcm = pmpll = pmmp = m/s bits = 1 , mcko = 0 ???? mpwr pin 0ma ? avdd=6.4ma(typ), dvdd=1.6ma(typ). ext slave mode (pmpll = m/s = mcko bits = 0 ) ? : avdd=5.7ma(typ), dvdd=1.3ma(typ). bypass mode (thr bit = 1 , pmadl = pmadr = m/s bits = 0 ), fs=8khz ? : avdd=1 ? a(typ), dvdd=150 ? a(typ). note 14 . ???? dvdd ? dvss ??r??
[ ak570 1 ] ms0404 - j - 04 2015/10 - 7 - ?? ( ta= 25 ? c ; avdd=2.4 ? 3.6v; dvdd=1.6 ? 3.6v; fs=4 4.1k hz ) parameter symbol m in . t yp . max . unit a dc digital filter (decimation lpf): passband ( note 15 ) ? ? ? ? ? ? adc digital filter (hpf): hpf1 - 0 bits = ? ? ? ?? fs ( ?????` ) ?? pb=20.0khz(@ ? 1.0db) 0.454 x fs ? (adc) 1khz ??? note 16 . ? ???W??????I? 16 ????` ??????rg? dc ( ta= 25 ? c ; avdd=2.4 ? 3.6v; dvdd=1.6 ? 3.6v ) parameter symbol m in . t yp . max . unit h igh - l evel i nput voltage except csp pin; 2.2v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? h ? cclk pin ??????? (typ. 100k ? )
[ ak570 1 ] ms0404 - j - 04 2015/10 - 8 - ? ( ta =25 ? c ; avdd=2.4 ? 3.6v; dvdd=1.6 ? 3.6v ; c l =2 0pf ) parameter symbol m in . t yp . max . unit pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pu lse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck output timing frequency except dsp mode 1 fs 7.35 - 48 khz dsp mode 1 ( note 18 ) fsd 14.7 - 96 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bclk output timing period bcko1 - 0 bit = bcko1 - 0 bit = duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % exl rck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? ? except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - n s pulse width high tbckh 0.4 x tbck - - ns pll slave mode (pll reference clock = exlrck pin) exlrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? ? except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns note 18 . ?? 7.35khz ? 48khz ?
[ ak570 1 ] ms0404 - j - 04 2015/10 - 9 - parameter symbol m in . t yp . max . unit pll s lave mode (pll reference clock = exbclk pin) exlrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? ? except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period pll3 - 0 bits = pll3 - 0 bits = pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns exlrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz d sp mode: pulse width high tlrckh tbck ? ? except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 4 8 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bclk output timing period bcko1 - 0 bit = bcko1 - 0 bit = duty cycle dbck - 50 - %
[ ak570 1 ] ms0404 - j - 04 2015/10 - 10 - parameter symbol m in . t yp . max . unit audio interface timing (dsp mode) master mode lrck ? ? ? lrck ? ? ? bclk ? ? bclk ? ? slave mode exlrck ? ? exlrck ? ? exbclk ? ? exbclk ? ? exbclk ? exbclk ? audio interface timing (left justified & i 2 s) master mode bclk ? ? lrck edge to sdto (msb) (except i 2 s mode) tlrd ? bclk ? ? slave mode exlrck edge to exbclk ? exbclk ? exlrck edge to sdto (msb) (except i 2 s mode) tlrd - - 80 ns exbclk ? 00 or 11 note 20 . msbs, bckp bits = 01 or 10 note 21 . ??? exlrck ? exbclk ? ???????
[ ak570 1 ] ms0404 - j - 04 2015/10 - 11 - parameter symbol m in . t yp . max . unit control interface t iming (csp pin = l ) cclk period tcck 142 - - ns cclk pulse width low tcckl 56 - - ns pulse width high tcckh 56 - - ns cdti setup time tcds 28 - - ns cdti hold time tcdh 28 - - ns csn edge to cclk ? ( note 22 ) tcss 50 - - ns cclk ? edge ( note 22 ) tcsh 50 - - ns control interface timing (csp pin = h ) cclk period tcck 142 - - ns cclk pulse width low tcc kl 56 - - ns pulse width high tcckh 56 - - ns cdti setup time tcds 28 - - ns cdti hold time tcdh 28 - - ns csn edge to cclk ? ( note 22 ) tcss 50 - - ns cclk ? edg e ( note 22 ) tcsh 50 - - ns power - down & reset timing pdn pulse width ( note 23 ) tpd 150 - - ns pmadl or pmadr ? hpf1 - 0 bits = hpf1 - 0 bits = hpf1 - 0 bits = ? csn ? cclk cclk ? ??????? note 23 . ak570 1 pdn pin = l ????? note 24 . pmadl bit ? pmadr bit ?? lrck ? ? ?
[ ak570 1 ] ms0404 - j - 04 2015/10 - 12 - ??? figure 2 . clock timing (pll/ext master mode) figu re 3 . audio interface timing (pll/ext master mode & dsp mode: msbs = 0 ) bclk 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%dvdd tbck tbckh tbckl 50%dvdd dbck = tbckh / tbck x 100 tbckl / tbck x 100 dmck = tmckl x fmck x 100 lrck 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 lrck bclk 50%dvdd sdto 50%dvdd tbsd dbck tdbf 50%dvdd tlrckh tbck msb bclk 50%dvdd (bckp = "0") (bckp = "1")
[ ak570 1 ] ms0404 - j - 04 2015/10 - 13 - figure 4 . audio interface timing (pll/ext master mode & dsp mode: msbs = 1 ) figure 5 . audio interface timing (pll/ext master mode & except dsp mode) lrck bclk 50%dvdd sdto 50%dvdd tbsd dbck tdbf 50%dvdd tlrckh tbck msb bclk 50%dvdd (bckp = "1") (bckp = "0") lrck 50%dvdd bclk 50%dvdd sdto 50%dvdd tbsd tmblr tbckl tlrd
[ ak570 1 ] ms0404 - j - 04 2015/10 - 14 - figure 6 . clock timing (pll slave mode; pll reference clock = exlrck or exbclk pin & dsp mod e; msbs = 0) figure 7 . clock timing (pll slave mode; pll reference clock = exlrck or exbclk pin & dsp mode; msbs = 1) 1/fs exlrck vih tlrckh vil tbck exbclk tbckh tbckl vih vil tblr exbclk vih vil (bckp = "0") (bckp = "1") 1/fs exlrck vih tlrckh vil tbck exbclk tbckh tbckl vih vil tblr exbclk vih vil (bckp = "1") (bckp = "0")
[ ak570 1 ] ms0404 - j - 04 2015/10 - 15 - figure 8 . clock timing ( pll slave mode; pll reference clock = mcki pin & except dsp mode) figure 9 . audio interface timing (pll slave mode & dsp mode; msbs = 0) 1/fclk mcki tclkh tclkl vih vil 1/fs exlrck vih vil tbck exbclk tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%dvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 exlrck exbclk sdto 50%dvdd tbsd tlrb tlrckh msb vil vih vil vih exbclk vil vih (bckp = "0") (bckp = "1")
[ ak570 1 ] ms0404 - j - 04 2015/10 - 16 - figure 10 . audio interface timing (pll slave mode, dsp mode; msbs = 1) figure 11 . clock timing (ext slave mode) exlrck exbclk sdto 50%dvdd tbsd tlrb tlrckh msb vil vih vil vih exbclk vil vih (bckp = "1") (bckp = "0") 1/fclk mcki tclkh tclkl vih vil 1/fs exlrck vih vil tbck exbclk tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100
[ ak570 1 ] ms0404 - j - 04 2015/10 - 17 - figure 12 . audio interface timing (pll/ext slave mode) exlrck vih vil tblr exbclk vih vil tlrd sdto 50%dvdd tlrb tbsd msb
[ ak570 1 ] ms0404 - j - 04 2015/10 - 18 - figure 13 . write command input timing (csp pin = l ) figure 14 . write data input timing (csp pin = l ) csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2
[ ak570 1 ] ms0404 - j - 04 2015/10 - 19 - figure 15 . write command input timing (csp pin = h ) figure 16 . write data input timing (csp pin = h ) csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2
[ ak570 1 ] ms0404 - j - 04 2015/10 - 20 - figure 17 . power down & reset timing 1 figure 18 . power down & reset timing 2 pmadl bit or pmadr bit tpdv sdto 50%dvdd tpd pdn vil
[ ak570 1 ] ms0404 - j - 04 2015/10 - 21 - Ch ??? ?? i/f `? 5 ?? ( table 1 and table 2 ) mode pmpll bit m/s bit pll3 - 0 bits figure pll master mode ( note 25 ) 1 1 see table 4 figure 19 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 4 figure 20 pll slave mode 2 (pll reference clock: exlrck or exbclk pin) 1 0 see table 4 figure 21 ext slave mode 0 0 x figure 22 ext master mode ( note 2 6 ) 0 1 x figure 23 note 25 . pll master mode O^?? m/s bit = 1 , pmpll bit = 0 , mcko bit = 1 ? mcko pin ??? ?? note 2 6 . ext master mode ??? figure 49 ?O table 1 . clock mode setting (x: don t care) mode mcko bit mcko pin mcki pin bclk pin, exbclk pin l rck pin, exlrck pin pll master mode 0 l pll3 - 0 bits xk xk xk xk ? xk xk xk ? xk xk dsp mode 1 ? lrck 2fs ? table 2 . clock pins state in clock mode ?`??`?`? ?`??`?`? m/s bit ? 1 ??` 0 ?`?` ? ak5701 ??`r (pdn pin = l ) ??`?`?`???` ? m/s bit 1 ????`???? m/s bit mode ??? ?
[ ak570 1 ] ms0404 - j - 04 2015/10 - 22 - pll ` pmpll bit = 1 ri???? pll fs3 - 0 bit, pll3 - 0 bit xk???? pll ?rg???? pmpll bit 0 ? 1 ?? ??????? table 4 ?? 1) pll mode O mode pll3 bit pll2 bi t pll1 bit pll0 bit pll ? ?? ? rg ? others others n/a note 28 . pll3 - 0 bits = 0110 1001 ` table 5 ? table 4 . setting of pll mode (fs: sampling frequency , n/a: not available ) 2) pll mode ??O mcki ?? table 5 O????xk?? mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 7.349918khz ( note 29 ) 5 0 1 0 1 11.025khz 11.024877khz ( note 29 ) 6 0 1 1 0 14.7khz 14.69984khz ( note 29 ) 7 0 1 1 1 22.05khz 22.04975khz ( note 29 ) 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 29.39967khz ( note 29 ) 15 1 1 1 1 44.1khz 44.0995khz ( note 29 ) (default) others ot hers n/a note 29 . pll3 - 0 bits = 1001 ?? table 5 . setting of sampling frequency at pmpll bit = 1 and reference clock=mcki pin (n/a: not available)
[ ak570 1 ] ms0404 - j - 04 2015/10 - 23 - exlrck or exbclk |~ ?b?c
fs3, fs2 bit [???<xb0??/?w zwi8 ( table 6 ) mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 x x 7.35khz d fs d 12khz 1 0 1 x x 12khz < fs d 24khz 2 1 x x x 24khz < fs d 48khz (default) others others n/a (x: don ? t care, n/a: not av ailable) table 6 . setting of sampling frequency at pmpll bit = 3 1 and reference=exlrck/exbclk v pll b????_x8z 1) pll master mode (pmpll bit = 3 1 , m/s bit = 3 1 ) gb???[ pmpll bit 3 0 ? 3 1 _ks? pll @??mr[b6?
bclk \ lrck c 3 l ??
mc ko bit = 3 1 b\a mcko pin ?}cg?[^8?<xb???@?i?rm mcko bit = 3 0 b?c
mcko pin c 3 l ??krm ( table 7 ) dsp mode 0, 1 _>8z
pmpll bit = 3 0 ? 3 1 0?_|~ pll @??ks?
bclk \ lrck c lch b1? _pakz??6?krm dsp mode 0, 1 [ msbs bit = 3 0 , b ckp bit = 3 1 rsc msbs bit = 3 1 , bckp bit = 3 0 b?
bclk ?6?b 1 $?% b 3 h ?@ 2 $?% 7f_?mz 1/(256fs) te%c^~rm ???<x??fm?cm? pmpll bit = 3 0 _mg\[????"gaby^ bclk, lrck ??ion_ 3 l ??iog\@[arm pll state mcko pin bclk pin lrck pin mcko bit = 3 0 mcko bit = 3 1 pmpll bit 3 0 ? 3 1 %$? 3 l output y 3 l output 3 l output pll unlock ( v0 ) 3 l output y y y pll lock 3 l output see table 9 see table 10 1fs output ( note 30 ) note 30 . dsp mode 1 b\a
lrck c 2fs [m table 7 . clock operation at pll master mode (pmpll bit = 3 1 , m/s bit = 3 1 ) 2) pll slave mode (pmpll bit = 3 1 , m/s bit = 3 0 ) gb???[c pmpll bit = 3 0 ? 3 1 _ks? pll @??mr[b6?
mcko ?}cg?[^8?<x b???@?i?rmqb?
pll @??m\ mcko pin ?} table 9 [4ei?s???@? i?rm#k
pll @????_^ws?
adc ?}cg?^1?@?i?ro? pll state mcko pin mcko bit = 3 0 mcko bit = 3 1 pmpll bit 3 0 ? 3 1 %$? 3 l output y pll unlock ( v0 ) 3 l output y pll lock 3 l output see table 9 table 8 . clock operation at pll slave mode (pmpll bit = 3 1 , m/s bit = 3 0 )
[ ak570 1 ] ms0404 - j - 04 2015/10 - 24 - pll master mode (pmpl l bit = 1 , m/s bit = 1 ) ? 11.2896mhz, 12mhz , 12.288mhz, 13mhz, 13.5mhz, 19.2mhz, 24mhz, 26mhz or 27mhz ? ? pll ? mcko, bclk, lrck ????? (mcko) ps1 - 0 bit ( table 9 ) O?? mcko b it on/off ?? bclk bcko1 - 0 bits ?? 32fs or 64fs xk???? ( table 10 ) figure 19 . pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 9 . mcko ? (pll ` , mcko bit = 1 ) bcko1 bit bcko0 bit bclk ? ? ak5701 dsp or ? p mcko bclk lrck sdto bclk lrck sdti mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz, 13mhz 13.5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz mclk
[ ak570 1 ] ms0404 - j - 04 2015/10 - 25 - v pll slave mode (pmpll bit = 3 1 , m/s bit = 3 0 ) mcki, exbclk or exlrck pin l ?i?????? =_ ?4?b pll _z ak5701 _20[^????#? bkrm pll b? =???c
pll3 - 0 bit _z0?mg\@[arm ( table 4 ) a) pll ?? ?? ak5701 dsp or ? p mcko exbclk exlrck sdto bclk lrck sdti mcki 1fs ? 32fs mclk 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz, 13mhz 13.5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz ak5701 dsp or ? p mcki exbclk exlrck sdto bclk lrck sdti 1fs 32fs, 64fs
[ ak570 1 ] ms0404 - j - 04 2015/10 - 26 - ext slave mode (pmpll bit = 0 , m/s bit = 0 ) pmpll bit 0 ??????`?` (ext slave mode) ? mcki pin pll j?? adc ?????`??`? codec ? i/f ?Q?? ??? mcki (256fs, 512fs or 1024fs), exbclk ( ? 32fs ), exlrck(fs) ? mcki exlrck ???????? mcki ? fs1 - 0 bit ?xk???? ( table 11 ) mode fs3 - 2 bits fs1 bit fs0 bit mcki input frequency sampli ng frequency range 0 x 0 0 256fs 7.35khz ? x 0 1 1024fs 7.35khz ? x 1 0 512fs 7.35khz ? x 1 1 256fs 7.35khz ? 0 , m/s bit = 0 ) r mcki ?O (x : don t care) adc (pmadl bit = 1 or pmadr bit = 1 ) ?? (mcki, exbclk, exlrck) ??? ????o???????????????^ ??????????`?B (pmadl=pmadr bits = 0 ) ?? figure 22 . ext slave mode ak5701 dsp or ? p mcki exbclk exlrck sdto bclk lrck sdti mcko 1fs ? 32fs mclk 256fs, 512fs or 1024fs
[ ak570 1 ] ms0404 - j - 04 2015/10 - 27 - ext master mode (pmpll bit = 0 , m/s bit = 1 , te3 - 0 bits = 0101 , tmaster bit = 1 ) figure 49 ????O??????` (ext master mode) ? mcki pin pll ?? adc ???????? mcki (256fs, 512fs or 1024fs) ? mcki ? fs1 - 0 bit ?xk???? ( table 12 ) mode fs3 - 2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz ? x 0 1 1024fs 7.35khz ? x 1 0 512fs 7.35khz ? x 1 1 256fs 7.35khz ? r mcki ?O (x: don t care) adc (pmadl bit = 1 or pmadr bit = 1 ) mcki ???? mc ki o? ??????????????^???? mcki ????`?B (pmadl=pmadr bits = 0 ) ?? figure 23 . ext master mode bcko1 bit bcko0 bit bclk ? ak5701 dsp or ? p mcki bclk lrck sdto bclk lrck sdti mcko 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs
[ ak570 1 ] ms0404 - j - 04 2015/10 - 28 - ?` thr bit = 1 , m/s bit = 0 , pmadl bit = 0 , pmadr bit = 0 ?? exlrck, exbclk, exsdti pins ???`??? lrck, bclk, sdto p ins ?`? thr bit = 1 , m/s bit = 0 pmadl bit = 1 or pmadr bit = 1 ?? exlrck, exbclk pins ? lrck, bclk pins ?` sdto pin adc ?`? thr bit m/s bit pmadl bit pmadr bit bclk/lrck sdto mode figure 0 0 00 l l power down (default) 01/10/11 l adc data slave mode 1 00 output l power down 01/10/11 output adc data master mode 1 0 00 exbclk/exlrck exsdti bypass mode figure 24 01/10/11 exbclk/exlrck adc data slave & bypass figure 25 1 00 n/a n/a n/a 01/10/11 output adc data master mode table 14 . bypass mode select (n/a: not available) figure 24 . bypass mode figure 25 . slave & bypass mode ak5701 dsp or ? p bclk lrck sdti lrck sdto 1fs bclk ? 32fs dsp or ? p lrck sdto 1fs bclk ? 32fs exbclk exlrck exsdti ak5701 dsp or ? p bclk lrck sdti lrck sdto 1fs bclk ? 32fs dsp or ? p lrck analog in 1fs bclk ? 32fs exbclk exlrck lin/rin
[ ak570 1 ] ms0404 - j - 04 2015/10 - 29 - `????`?`?? 4 N?`?`?? ( table 15 ) dif1 - 0 bit xk???`?? msb ?`? 2 s ??`?`????`????`?? `??`?`??? ? dsp mode 1 pll master mode ????`?? lrck, bclk, sdto ? `?`?? exlrck, exbclk, sdto ??? mode 2 mode 3 ? sdto bclk/exbclk ? ?? mode dif1 bit dif0 bit sdto bclk, exbclk figure 0 0 0 dsp mode 0 32fs see table 16 1 0 1 dsp mode 1 ? ?? ? 2 s Q ? ` 0, 1) ?? bckp, msbs bit ??`? i/f ?????? ? bckp bit = 0 ?? sdto bclk/exbclk ? ?? bckp bit = 1 ?? sdto bclk/exbclk ? ?? msbs bit ? msb ?`? bclk/exbclk ????????? dif1 dif0 msbs bckp audio interface format 0 0 0 0 sdto ?` ? ? ? ?? ?` ? ? ? ?? ?` ? ? ? ? ? ? ?` ? ? ? ? ? ? ?` ? ? ? ?? ?` ? ? ? ?? ?` ? ? ? ? ? ? ?` ? ? ? ? ? ? ? 16bit ?` 8bit ?`?Q? 16bit ?`g?? 16bit ?` ? 1 8bit ?` ? 1 Q? 8bit ?` ? 1 dac ?? 16bit ?` ?Q C 256 ???????? 8bit ?`?Q?? 16bit ?`?? ? (128) ????X?
[ ak570 1 ] ms0404 - j - 04 2015/10 - 30 - figure 26 . mode 0 timing (bckp = 0 , msbs = 0 , m/s = 0 or 1 ) figure 27 . mode 0 timing (bckp = 1 , msbs = 0 , m/s = 0 or 1 ) figure 28 . mode 0 timing (bckp = 0 , msbs = 1 , m/s = 0 or 1 ) figure 29 . mode 0 timing (bckp = 1 , msbs = 1 , m/s = 0 or 1 ) exlrck lrck 31 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 2 1 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 2 1 0 14 15 2 1 0 14 lch lch rch rch exbclk(32fs) bclk(32fs) sdto(o) 31 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 2 1 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 2 1 0 14 15 2 1 0 14 lch lch rch rch exlrck lrck exbclk(32fs) bclk(32fs) sdto(o) 31 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 2 1 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 2 1 0 14 15 2 1 0 14 lch lch rch rch exlrck lrck exbclk(32fs) bclk(32fs) sdto(o) 31 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 1 5 8 2 1 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 2 1 0 14 15 2 1 0 14 lch lch rch rch exlrck lrck exbclk(32fs) bclk(32fs) sdto(o)
[ ak570 1 ] ms0404 - j - 04 2015/10 - 31 - figure 30 . mode 1 timing (bckp = 0 , msbs = 0 , m/s = 1 ) figure 31 . mode 1 timing (bckp = 1 , msbs = 0 , m/s = 1 ) figure 32 . mode 1 timing (bckp = 0 , msbs = 1 , m/s = 1 ) figure 33 . mode 1 timing (bckp = 1 , msbs = 1 , m/s = 1 ) lrck bclk(32fs) sdto(o) 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 15 5 8 8 7 1 4 3 10 13 2 6 0 15 5 8 8 7 1 4 3 2 6 13 10 0 2 14 14 2 bclk(64fs) sdto(o) 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 2 1 0 13 16 15:msb, 0:lsb 2 14 14 2 1/fs lch lch rch rch 15 0 31 lrck bclk(32fs) sdto(o) 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 15 5 8 8 7 1 4 3 10 13 2 6 0 15 5 8 8 7 1 4 3 2 6 13 10 0 2 14 14 2 bclk(64fs) sdto(o) 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 2 1 0 13 16 15:msb, 0:lsb 2 14 14 2 1/fs lch lch rch rch 15 0 31 lrck bcl k(32fs) sdto(o) 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 15 5 8 8 7 1 4 3 10 13 2 6 0 15 5 8 8 7 1 4 3 2 6 13 10 0 2 14 14 2 bclk(64fs) sdto(o) 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 2 1 0 13 16 15:msb, 0:lsb 2 14 14 2 1/fs lch lch rch rch 15 0 31 lrck bclk(32fs) sdto(o) 0 1 8 8 9 11 12 14 15 0 1 8 8 9 11 12 14 15 0 15 5 8 8 7 1 4 3 10 13 2 6 0 15 5 8 8 7 1 4 3 2 6 13 10 0 2 14 14 2 bclk(64fs) sdto(o) 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 2 1 0 13 16 15:msb, 0:lsb 2 14 14 2 1/fs lch lch rch rch 15 0 31
[ ak570 1 ] ms0404 - j - 04 2015/10 - 32 - figure 34 . mode 2 ? ( ?? , m/s = 0 or 1 ) figure 35 . mode 3 ? (i 2 s , m/s = 0 or 1 ) ??? pmadl, pmadr, mix bits O? adc ?`?????? ?`? alc (alc bit = 1 ) ???? ` (alc bit = 0 ) ? pmadl bit pmadr bit mix bit adc lch data adc rch data 0 0 x all ??? (x: don t care) 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 8 7 6 0 3 2 11 14 1 5 15 14 4 8 7 6 0 3 2 1 5 14 11 15 13 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 14 1 2 2 1 15 15:msb, 0:lsb lch data rch data 2 1 13 16 0 16 3 13 3 13 13 3 exlrck lrck exbclk(32fs) bclk(32fs) sdto(o) exbclk(64fs) bclk(64fs) sdto(o) 0 1 2 4 9 10 12 13 15 0 1 2 4 9 10 12 13 15 0 0 1 15 5 13 7 7 1 4 3 11 14 2 6 0 15 5 13 7 7 1 4 3 2 6 14 11 0 13 0 1 2 3 14 15 17 18 31 0 1 2 4 14 15 17 18 31 0 1 15 0 15 13 2 1 15:msb, 0:lsb lch data rch data 2 1 14 16 0 16 3 14 14 3 2 14 3 4 exlrck lrck exbclk(32fs) bclk(32fs) sdto(o) exbclk(64fs) bclk(64fs) sdto(o)
[ ak570 1 ] ms0404 - j - 04 2015/10 - 33 - ? ak5701 dc ?????? hpf i?? hpf ??? hpf1 - 0 bits xk ??????? (fs) ??? 3.4hz (@fs= 44.1khz) ? hpf1 bit hpf0 bit fc fs=44.1khz fs=22.05kh z fs=11.025khz 0 0 3.4hz 1.7hz 0.85hz (default) 0 1 6.8hz 3.4hz 1.7hz 1 0 13.6hz 6.8hz 3.4hz 1 1 n/a n/a n/a table 18 . ? hpf ??? (n/a: not available) ?? ak5701 ?i?? mdif1, mdif2 bit = 0 ? inl, inr bit ?? lin1/lin2, rin1/rin2 ??????? mdif1, mdif2 bit = 1 ? lin1, rin1, lin2, rin2 pin ?? lin+, lin ? , rin ? , rin+ pin ????? ( figure 37 ) mdif1 bit mdif2 bit inl bit inr bit lch rch 0 0 0 0 lin1 rin1 (default) 1 lin1 rin2 1 0 lin2 rin1 1 lin2 rin2 1 0 x lin1 rin+/ ? ? ? ? t care, n/a: not available) figure 36 . ? ? lin1/lin+ pin adc lch rin1/ lin ? pin inl bit mdif1 bit rin2/ rin+ pin adc rch lin2/ rin ? pin inr bit mdif2 bit ak5701
[ ak570 1 ] ms0404 - j - 04 2015/10 - 34 - figure 37 . ??? (mdif1/2 bits = 1 ) ???? ak5701 ??????i?? mgain1 - 0 bit ??O???? ( table 20 ) ?`?? mgain1 - 0 bit s = 00 ? typ. 60k ? mgain1 - 0 bits = 01 , 10 ? typ. 30k ? ? mgain1 bit mgain0 bit input gain 0 0 0db 0 1 +15db (default) 1 0 +30db 1 1 n/a table 20 . ? (n/a: not available) ??` pmmp bit = 1 ? mpwr pin ????o?????R (0.75 x avdd)v (typ) ????? min. 0.5k ? ???? 2 ?y???? min. 2k ? ? mpwr pin ??????A? ( figure 38 ) pmmp bit mpwr pin 0 hi - z (default) 1 output table 21 . ??` figure 38 . mic block circuit in1 ? pin in1+ pin mpwr pin ak5701 mic - amp 1k 1k mpwr pin ? 2k ? mic power microphone lin1 pin microphone rin1 pin microphone lin2 pin microphone rin2 pin ? 2k ? ? 2k ? ? 2k ?
[ ak570 1 ] ms0404 - j - 04 2015/10 - 35 - alc alc bit = 1 ? alc ???? alc ? 1. alc ?? alc ??? lch, rch ??a?? alc ???O? ( table 22 ) ? ? lmat1 - 0 bit O ( table 23 ) ivl, ivr (l/r ? ) ????p?? zelmn bit = 0 ( ???? ) ? alc ??? ivl, ivr ? l/r ????????????????rg alc ?rg??? ztm1 - 0 bit ?O?? ( table 24 ) zelmn bit = 1 ( ???o ) ? alc ??? ivl, ivr ?r ( : 1/fs) ???p? lmat1 - 0 bit O?o 1 step ?? p?K? alc bit 0 ???????? alc ????? p?R?? lmth1 lmth0 alc ?? ? ?C?????? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???? ?C?????? zelmn lmat1 lmat0 alc ?? ?? ?? att ???O (x: don t care) ztm1 ztm0 ????rg ????rgO
[ ak570 1 ] ms0404 - j - 04 2015/10 - 36 - 2. alc ? alc ?? wtm1-0 O?rg ( table 25 ) Cg?? alc ? C?????? ( table 22 ) ??? alc ?? alc ? O? ? ( table 27 ) ? ztm1-0 Org ( table 24 ) ???? ? rgain1 - 0 bit O ( table 26 ) ivl, ivr ( l/r ? ) ????? alc wtm1-0 O?? wtm1 - 0 O ztm1 - 0 OL ????? ztm1 - 0 ? alc ?? F? ivl, ivr 30h ?? rgain1 - 0 bit = 01 (2 steps) O?? alc ? ?? ivl, ivr 32h ? 0.75db(0.375db x 2) ?? ivl, ivr ?? (ref7 - 0) _? ivl, ivr ??? ? alc ?C ( ?C?????? ) ? output signal < ( ???? ) ?????C??????? ( ?C?????? ) > output signal ???rCrg?_?? ? alc ??????? alc ???????? ????????? ? g????????????????? wtm1 wtm0 alc ? ? ? ?CrgO rgain1 r gain0 gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 26 . alc ??O ref7 - 0 gain(db) step f1h + 36 .0 0.375db f0h + 35.625 efh + 35.2 5 : : e2h + 30.375 e1h + 30 .0 (default) e0h + 29.625 : : 0 3 h ? ? ? ?r?O
[ ak570 1 ] ms0404 - j - 04 2015/10 - 37 - 3. alc O table 28 ?h??? alc O? register name comment fs=8khz fs=44.1khz data operation data operation lmth limiter detection level 01 ? ? O alc ?R???????????? alc K (alc bit = 0 ? pmadl = pmadr bits = 0 ) ?? ? lmth, lmat1 - 0, wtm1 - 0, ztm1 - 0, rgain 1 - 0, ref7 - 0, zelmn ?? note : wr : write figure 39 . alc O manual mode * the value of ivol should b e the same or smaller than ref s wr (ztm1 - 0, wtm1 - 0) wr (ref7 - 0) wr (ivl/r7 - 0) wr (lmat1 - 0, rgain1 - 0, zelmn, lmth1 - 0; alc= 1 ) example: limiter = zero crossing enable recovery cycle = 16ms@8khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = 1 (1) addr=18h&19h, data=91h (2) addr=1ah, data=00h (3) addr=1bh, data=e1h alc operation (4) addr=1ch, data=81h
[ ak570 1 ] ms0404 - j - 04 2015/10 - 38 - ??` ??`?r alc bit = 0 ???`???`????`?? ??? 1. ???? alc v?O (ztm1 - 0, lmth ? ) 2. ????Z????? alc v? ? 3. ??`???`???? ??` ivl7 - 0, ivr7 - 0 bit O? ( table 29 ) ?`r l/r ?????????rg ztm1 - 0 bit O??? pmadl = pmadr bits = 0 ? ivl7 - 0, ivr7 - 0 bits ?z?? pmadl bit = 1 or pmadr bit = 1 ?Q? adc ??O ivol _?? ivl7 - 0 ivr7 - 0 gain ( db) step f1h + 36 .0 0.375db f0h + 35.625 efh + 35.25 : : 92h + 0.375 91h 0 .0 (default) 90h ? ? ? ? ??`O
[ ak570 1 ] ms0404 - j - 04 2015/10 - 39 - ivl7 - 0, ivr7 - 0 bit z?A??????rg?g??? g???z???????????`? ???z?? ?????z?o???? ????????????rg?gz??? ? figure 40 . alc ivol (1) alc _?r ivl ivr ?????? ivl ?`???? alc bit = 1 z? ivl7 - 0 bits ? alc _???rg ??Crg (wtm1 - 0 bits) + ????rg (ztm1 - 0 bits) ? (2) alc ? ivl, ivr ? (18h, 19h) ?z?????? alc disable ?????????r????? alc enable ?? alc bit = 0 ?????rg?g? alc bit = 1 O ??? ??r?? p dn pin ? l ????????? ? ak5701 ???????? pmadl=pmadr bits = 0 ?B pmadl bit ? pmadr bit 0 ? 1 ??? adc ??_??? hpf1 - 0 bits = 00 ? 3088/fs=70.0ms@fs=44.1khz ? ( table 30 ) ? adc ?` 2 s ?? 0 ??K? adc ???????`????? hpf1 bit hpf0 bit init cycle cycle fs=44.1khz fs=22.05khz fs=11.025khz 0 0 3088/fs 70.0ms ( ?X ?X ?X ?O (n/a: not available) alc bit alc status disable enable disable ivl7 - 0 bits e1h(+30db) ivr7 - 0 bits c6h(+20db) internal ivl e1h(+30db) e1(+30db) -- > f1(+36db) e1(+30db) inter nal ivr c6h(+20db) e1(+30db) -- > f1(+36db) c6h(+20db) (1) (2)
[ ak570 1 ] ms0404 - j - 04 2015/10 - 40 - ???`????` ?O 3 ?? i/f ? ( csn, cclk, cdti ) z?? csp pin O? csn pin O? chip address ? 1) csp pin = l ? i/f ??` chip address (2bits , 10 ? ), read/write (1bit , 1 ? ), register address (msb first, 5 bits) control data (msb first, 8bits) ???`?? cclk ? ?????? ? ?z???`z? csn ? 16 ? cclk ? ???? 1 ??? z? c sn ? h ?? cclk ??`? 7 mhz (max) ? pdn pin = l ??????? figure 41 . ???`????`? (csp pin = l ) 2) csp pin = h ? i/f ??` chip address (2bits , 01 ? ), read/write (1bit , 1 ? ), register address (msb first, 5 bits) control data (msb first, 8bits) ???`?? cclk ? ?????? ? ?z?? ?`z? csn ? 16 ? cclk ? ???? 1 ??? z? csn ? l ?? cclk ??`? 7 mhz (max) ? pdn pin = l ??????? figure 42 . ???`????`? (csp pin = h ) csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti c1 c0 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w c1 - c0: chip address (c1 = 0 , c0 = cad1 ) ; fixed to 01 r/w: read/wri te ( 1 : write, 0 : read); fixed to 1 a4 - a0: register address d7 - d0: control data clock, h or l h or l clock, h or l h or l csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 cdti c1 c0 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w c1 - c0: chip address (c1 = 1 , c0 = cad0) ; fixed to 10 r/w: read/wri te ( 1 : write, 0 : read); fixed to 1 a4 - a0: register address d7 - d0: control data clock, h or l h or l clock, h or l h or l
[ ak570 1 ] ms0404 - j - 04 2015/10 - 41 - ??? addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 0 0 0 0 0 pmvcm pmadr pmadl 11h pll control 0 0 pll3 pll2 pll1 pll0 m/s pmp ll 12h signal select 0 0 0 pmmp mdif2 mdif1 inr inl 13h mic gain control 0 0 0 0 0 0 mgain1 mgain0 14h audio format select 0 0 1 mix msbs bckp dif1 dif0 15h fs select hpf1 hpf0 bcko1 bcko0 fs3 fs2 fs1 fs0 16h clock output select 0 0 0 0 thr mcko ps1 p s0 17h volume control 0 0 0 0 0 0 0 ivolc 18h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 19h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 1ah timer select 0 0 0 0 ztm1 ztm0 wtm1 wtm0 1bh alc mode control 1 re f7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 1ch alc mode control 2 alc zelmn lmat1 lmat0 rgain1 rgain0 lmth1 lmth0 1dh mode control 1 te3 te2 te1 te0 0 0 0 0 1eh mode control 2 0 0 0 0 0 0 tmaster 0 note 31 . pdn pin l ???? ? note 32 . 0 ?????? 1 z???? 1 ?????? 0 z ?????? 10h - 1eh ?z????
[ ak570 1 ] ms0404 - j - 04 2015/10 - 42 - ?h addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 0 0 0 0 0 pmvcm pmadr pmadl default 0 0 0 0 0 0 0 0 pmadl: mic - amp lch, adc lch ?`?? 0: power down ( default) 1: power up pmadr: mic - amp rch, adc rch ?`?? 0: power down (default) 1: power up pmadl ? pmadr bit 0 1 ?? (3088/fs=70.0ms@fs= 44.1khz, hpf1 - 0 bits = 00 ) _? ?K? adc ??`? pmvcm: vcom ?`?? 0: power down (default) 1: power up ????? pmvcm bit 1 ???? pmvcm bit ? 0 z???? pmadl, pmadr, pmpll, pmmp, mcko bits 0 ?r ? ????? on/off ( 1 / 0 ) ???????` ??????? pdn pin l ??????vS??????`????? ????? ? pmvcm, pmadl, pmadr, pmpll, mcko bits ??? 0 ?????????` ?????????????M 20 ? a(typ) ?? ???? (typ. 1 ? a) ? pdn pin = l ? adc ? ?????o??? adc ???????o addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h pll control 0 0 pll3 pll2 pll1 pll0 m/s pmpll default 0 0 1 0 0 1 0 0 pmpll: pll ?`?? 0: ext mode and power down (default) 1: pll mode and power up m/s: master / slave mode xk 0: slave mode (default) 1: master mode pll3 - 0: pll ??xk ( table 4 ) default: 1001 (mcki pin=12mhz)
[ ak570 1 ] ms0404 - j - 04 2015/10 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h signal select 0 0 0 pm mp mdif2 mdif1 inr inl default 0 0 0 0 0 0 0 0 inl: adc lch `xk 0: lin1 pin (default) 1: lin2 pin inr: adc rch `xk 0: rin1 pin (default) 1: rin2 pin mdif1: adc lch ?O 0: ??? (lin1/lin2 pin: d efault) 1: (lin+/lin ? pin ) mdif2: adc rch ?O 0: ??? (rin1/rin2 pin: d efault) 1: (rin+/rin ? pin) pmmp: mpwr pin ?`?? 0: power down: hi - z (default) 1: power up addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h mic gain control 0 0 0 0 0 0 mgain1 mgain0 def ault 0 0 0 0 0 0 0 1 mgain1 - 0: ?????` ( table 20 ) default: 01 (+15db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 14h audio format select 0 0 1 mix msbs bckp dif1 dif0 default 0 0 1 0 0 0 1 1 dif1 - 0 : `????`?`?? ( table 15 ) default: 11 (i 2 s) bckp: dsp mode r bclk/exbclk OO ( table 16 ) 0 : ? sdto (default) 1 : ? sdto msbs: dsp mode r lrck/exlrck O ( table 16 ) 0 : lrck/exlrck ? ? bclk/exbclk ? (default) 1 : lrck/exlrck ? ? bclk/exbclk 1 ? mix: adc ?` ( table 17 ) 0 : normal operation (default) 1 : (l+r)/2
[ ak570 1 ] ms0404 - j - 04 2015/10 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 15h fs select hpf1 hpf0 bcko1 bcko0 fs3 fs2 fs1 fs0 default 0 0 0 1 1 1 1 1 fs3 - 0: ???<x ( table 5 and table 6 ) lg mcki ?<xb 0? ( table 11 ) default: 3 1111 (44.1khz) pll ???c???<xb0??/?8
ext ???c mcki b ??<x?0?kr m bcko1 - 0: e????b bclk ??<xb0? ( table 10 ) default: 3 01 (32fs) hpf1 - 0: ??-o???-y h pf ?o???<x>|g adc 6???y0? ( table 18 , table 30 ) default: 3 00 (fc=3.4hz@fs=44.1khz, init cycle=3088/fs) addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h clock output select 0 0 0 0 thr mcko ps1 ps0 default 0 0 0 0 0 0 0 0 ps1 - 0: mcko ?<xb0? ( table 9 ) default: 3 00 (256fs) mcko: mcko ??bd? 0: disable: mcko pin = 3 l (default) 1: enable: output frequency is selected by ps1 - 0 bits. thr: ???????0? ( table 14 ) 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 17h volume control 0 0 0 0 0 0 0 ivolc default 0 0 0 0 0 0 0 1 ivolc: ivol b?o??y 0: independent 1: dependen t (default) ivolc bit = 3 1 b\a
ivl7 - 0 bit [g3??yb ivol @?krm#k
ivr7 - 0 bit _ ivl7 - 0 bit bcia3?r?ro? addr register name d7 d6 d5 d4 d3 d2 d1 d0 18h lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 19h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 default 1 0 0 1 0 0 0 1 ivl7 -0 , ivr7 - 0 : ?1?ay?? ; 0.375db step, 242 level ( table 29 ) default: 3 91h (0db)
[ ak570 1 ] ms0404 - j - 04 2015/10 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ah timer select 0 0 0 0 ztm1 ztm0 wtm1 wtm0 default 0 0 0 0 0 0 0 0 wtm1 - 0: alc ?CrgO ( table 25 ) default: 00 (128/fs) alc ???k????O? ztm1 - 0: alc ????rgO ( table 24 ) default: 00 (128/fs) ?z? alc ????????? ?????? addr register name d7 d6 d5 d4 d3 d2 d1 d0 1bh alc mode control 1 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref 7 -0 : alc ?r?O 0.375 db step, 242 level ( table 27 ) default: e1h (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch alc mode control 2 alc zelmn lmat1 lmat0 rgain1 rgain0 lmth1 lmth0 default 0 0 0 0 0 0 0 0 lmth1 - 0: alc ?? ?O? / ?C?????? ( table 22 ) default: 00 rgain1 - 0: alc ?????? ( table 26 ) default: 00 lmat1 - 0: alc ?? att ?? ( table 23 ) default: 00 zelmn: alc ??r????`? 0: enable (default) 1: disable alc: alc ?`? 0: alc disable (default) 1: alc enable
[ ak570 1 ] ms0404 - j - 04 2015/10 - 46 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 1dh mode control 1 te3 te2 te1 te0 0 0 0 0 default 1 0 1 0 0 0 0 0 te3 - 0: ext master mode enable 0101 z 1eh ?z????? ext master mode `?? 1010 O 1010 , 0101 O?? default: 1010 addr register name d7 d6 d5 d4 d3 d2 d1 d0 1eh mode control 2 0 0 0 0 0 0 tmaster 0 default 0 0 0 0 0 0 0 0 tmaster: ext master mode ????z? te3 - 0 bits = 0101 ??? 0: except ext master mode (default) 1: ext master mode
[ ak570 1 ] ms0404 - j - 04 2015/10 - 47 - ?O? figure 43 figure 44 ???A? ???y???u?` (akd5701) ? note: - ak5701 avss, dvss x?`???? - ???`??? - ext ` (pmpll bit = 0 ) ?? vcoc pin ?`?? - pll ` (pmpll bit = 1 ) ?? cp rp table 4 ?? cp+rp ?K 0.1 x cp ?A????? - 100ms ?h_????? ac ??????? 1 ? f ? figure 43 . ??A ( ?r ) mpwr rin2 lin2 rin1 lin1 vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck ak5701 top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 2 3 4 5 6 2.2k 2.2k 2.2k 2.2k external mic internal mic 0.1u 2.2u 0.1u power supply 2.4 ? 3.6v dsp ? p rp analog ground digital gr ound r1 r2 0.1u 10u 10u power supply 1.6 ? 3.6v cp 0.1 x cp (note) dsp ? 1u ? 1u ? 1u ? 1u
[ ak570 1 ] ms0404 - j - 04 2015/10 - 48 - note: - ak5701 avss, dvss x?`???? - ???`??? - ext ` (pmpll bit = 0 ) ?? vcoc pin ?`?? - pll ` (pmpll bit = 1 ) ?? cp rp table 4 ?? cp+rp ?K 0.1 x cp ?A????? figure 44 . ?A ( r ) mpwr rin2 lin2 rin1 lin1 vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck ak5701 top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 2 3 4 5 6 line in 0.1u 2.2u 0.1u power supply 2.4 ? 3.6v dsp ? p rp analog ground digital ground r1 r2 0.1u 10u 10u power supply 1.6 ? 3.6v cp 0.1 x cp (note) dsp
[ ak570 1 ] ms0404 - j - 04 2015/10 - 49 - 1. ????? ?????????? avdd, dvdd ????????o ? avdd, dvdd e??o?????`??????? avss, dvss ??????A????????? pc ?`??????A??????????? ????A 2. ?R avdd pin ?R????O?? avdd avss g 0.1 ? f ? ????A? vcom ??????R??????? ?? 2.2 ? f ????????K 0.1 ? f ????? avss ?g ?A??????????????A vcom pin ?????????????{? ??????? vcom pin ?x 3. ?? ????????????? ? 60k ? (typ)@mgain1 - 0 bits = 00 , 30k ? (typ)@mgain1 - 0 bits = 01 or 10 ? ????R (0.5 x avdd) ? 0.6 x avdd vpp(typ)@mgain 1 - 0 bits = 00 ?????????? dc ?? r??? fc=1/(2 ? rc) ? `??`??? 2 s ? (2 a ) ? dc ?? (adc dc ???? ) i hpf(fc=3.4hz@hpf1 - 0 bits = 00 , fs=44.1khz) ? ???? ak5701 ?????? avss avdd ???R??? ?
[ ak570 1 ] ms0404 - j - 04 2015/10 - 50 - ?`?` ?O adc power - up r???o??? 1. pll ?`?? figure 45 . clock set up sequence ( 1) < > (1) ??? pdn pin l ? h g ak5701 ???? 150ns ? l g?? (2) g? dif1 - 0, pll3 - 0, fs3 - 0, bcko1 - 0, m/s bits O??? (2a) m/s bit = 1 , pll3 - 0, fs3 - 0, bcko1 - 0 O (2b) dif1 - 0 O (3) vcom ?`? : pmvcm bit = 0 ? 1 ???? vcom ? (4) mcko ?? : mcko bit = 1 mcko ??? : mcko bit = 0 (5) pmpll bit = 0 ? 1 O mcki pin ??o? pll `?? pll ?rg mcki=12mhz ? 40ms(max) ? ( table 4 ) (6) pll ? bclk, lrck ???_?? (7) mcko bit = 1 ??g? mcko pin ???? (8) mcko bit = 1 ?? pll mcko pin ??? bclk pin lrck pin mcko bit (addr:16h, d2) pmpll bit (addr:11h, d0) 40msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin (5) (4) input m/s bit (addr:11h, d1) mcko pin output (8) (7) 40msec(max) example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = l ? h (3)addr:10h, data:04h (2)addr: 11h, data:12h addr:14h, data:23h addr:15h, data:2fh (4)addr:16h, data:04h addr:11h, data:13h mcko, bclk and lrck output
[ ak570 1 ] ms0404 - j - 04 2015/10 - 51 - 2. pll `?` ??? (exlrck or exbclk pin) ?? figure 46 . clock set up sequence ( 2) < > (1) ??? pdn pin l ? h g ak5701 ???? 150ns ? l g?? (2) g? dif1 - 0, fs3 - 0, pll 3 - 0 bits O? (3) vcom ?`? : pmvcm bit = 0 ? 1 ???? vcom ? (4) pmpll bit = 0 ? 1 O pll ?? (exlrck or exbclk pin) o?? pll `?? pll ?rg exlrck pll ???? 160ms(max), exbclk pll ?? vcoc pin ? 10k+4.7nf ?? 2ms( max) ? ( table 4 ) (5) pll ??_?? pmpll bit (addr:11h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) (5) input 4fs of example: audio i/f format : i2s pll reference clock: exbclk exbclk frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = l ? h (3) addr:10h, data:04h (2) addr:11h, data:0ch addr:14 h, data:23h addr:15h, data:2fh (4) addr:11h, data:0dh
[ ak570 1 ] ms0404 - j - 04 2015/10 - 52 - 3. pll `?`??? (mcki pin) ?? figure 47 . clock set up sequence ( 3) < > (1) ? ? pdn pin l ? h g ak5701 ???? 150ns ? l g?? (2) g? dif1 - 0, pll3 - 0, fs3 - 0, bcko1 - 0, m/s bits O? (3) vcom ?`?? pmvcm bit = 0 ? 1 ???? vcom ? (4) mcko O : mcko bit = 1 (5) pmpll bit = 0 ? 1 O m cki pin ??o?? pll `?? pll ?rg mcki=12mhz ? 40ms(max) ? ( table 4 ) (6) pll ? mcko pin ??? (7) g?? mcko pin ???? (8) mcko ??? exbclk, exlrck ?? exbclk pin exlrck pin mcko bit (addr:16h, d2) pmpll bit (addr:11h, d0) (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 40msec(max) (8) input example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = l ? h (3)addr:10h, data:04h (2)addr:11h, dat a:10h addr:14h, data:23h addr:15h, data:2fh (4)addr:16h, data:04h addr:11h, data:11h mcko output start exbclk and exlrck input start
[ ak570 1 ] ms0404 - j - 04 2015/10 - 53 - 4. ?? `??? ( `?` ) figure 48 . clock set up sequence ( 4) < > (1) ??? pdn pin l ? h g ak5701 ???? 150ns ? l g?? (2) g? dif1 - 0, fs1 - 0 bits O? (3) vcom ?`?? pmvcm bit = 0 ? 1 ???? vcom ? (4) mcki, exlrck, exbclk ???_?? (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) input (4) mcki pin input example: : audio i/f format: i2s input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = l ? h (3) addr:10h, data:04h (2) addr:11h, data:00h addr:14h, data :23h addr:15h, data:2fh mcki, exbclk and exlrck input
[ ak570 1 ] ms0404 - j - 04 2015/10 - 54 - 5. ??`??? ( ?` ) figure 49 . clock set up sequ ence ( 5) < > (1) ??? pdn pin l ? h g ak5701 ???? 150ns ? l g?? (2) g? dif1 - 0, fs1 - 0, bcko1 - 0, m/s, te3 - 0, tmaster bits O??? (2a) m/s bit = 1 , fs3 - 0, bcko1 - 0 O (2b) dif1 - 0 O (2c) te3 - 0 bits = 0101 (2d) tmast er bit = 1 : bclk, lrck _?? (3) vcom ?`?? pmvcm bit = 0 ? 1 ???? vcom ? ext master mode ??`???? pdn pin = l ? h ?? te3 - 0 bits = 1010 z? table 1 ????O? te3-0 bits (addr:1dh, d7-4) "0101" (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin input m/s bit (addr:11h, d1) bclk pin lrck pin output tmaster bit (addr:1eh, d1) "1010" example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select: 256fs sampling frequency: 44.1khz (1) power supply & pdn pin = l ? h (3)addr:10h, data:04h (2)addr:11h, data:26h addr:14h, data:23h addr:15h, data:2fh addr:1dh, data:50h addr:1eh, data:02h bclk and lrc k output
[ ak570 1 ] ms0404 - j - 04 2015/10 - 55 - 6. ` & ?`?? figure 50 . clock set up sequence ( 6) < > (1) ??? pdn pin l ? h g ak5701 ???? 150ns ? l g?? (2) g? thr bit = 1 dif1 - 0, fs3 - 0, pll3 - 0 bits O? (3) vcom ?`? : pmvcm bit = 0 ? 1 ???? vcom ? (4) pmpll bit = 0 ? 1 O pll ?? (exlrck or exbclk pin) o?? pll `?? pll ?rg exlrck pll ???? 160ms(max), exbclk pll ?? vcoc pin ? 10k+4.7nf ?? 2ms(m ax) ? ( table 4 ) (5) pll ??_?? pmpll bit (addr:11h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) (5) input 4fs of example: audio i/f format : i2s pll reference clock: exbclk exbclk frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = l ? h (3) addr:10h, data:04h (2) addr:11h, data:0ch addr:14 h, data:23h addr:15h, data:2fh addr:16h, data:08h (4) addr:11h, data:0dh
[ ak570 1 ] ms0404 - j - 04 2015/10 - 56 - 7. ?`?? figure 51 . clock set up sequence ( 7) < > (1) ??? pdn pin l ? h g ak5701 ???? 150ns ? l g?? (2) thr bit = 1 O (3) exlrck, exbclk, exsdti ? lrck, bclk, sdto _?? (1) power supply pdn pin thr bit (addr:16h, d3) (2) exlrck pin exbclk pin exsdti pin (3) input (1) power supply & pdn pin = l ? h (2) addr:16h, data:08h mcki, exbclk and exlrck input
[ ak570 1 ] ms0404 - j - 04 2015/10 - 57 - ?h ?? figure 52 . mic input recording seque nce < > fs=44.1khz r alc O? alc ?`?? figure 39 . alc O ? ?O?????o (1) ?? (fs3 - 0 bits) O pll `????? ? pll ?rg??] (6) ? adc ?`??? (2) ? ( ?? 12h&13h) O (3) alc timer ( ?? 1ah) O (4) alc ref ( ?? 1bh) O (5) lmth1 - 0, rgain1 - 0, lmat1 - 0, alc bits O ( ?? 1ch) (6) ? adc ?`? : pmadl = pmadr bits = 0 ? 1 adc ? 3088/fs=70.0ms@fs=44.1khz, hpf1 - 0 bits = 00 ? alc ??` (ivl/r7 - 0 bits) ? (0db) _?? 100ms ?h_?? pmvcm=pmmp bits = 1 O 2ms pmpll bit = 1 O 6ms pmadl=pmadr bits = 1 O (7) ? adc ?` : pmadl = pmadr bits = 1 ? 0 ? adc ?`???? alc disable ?B????? alc O????` (al c bit = 0 ) ??? adc ` (pmadl = pmadr bits = 0 ) ??? pmadl = pmadr bits = 0 ???` (ivl/r7 - 0 bits) ??????`??r ??`?O?_?? (8) alc disable: alc bit = 1 ? 0 fs3-0 bits (addr:15h, d3-0) mic control (addr:12h, d4 & addr:13h, d1-0) pmadl/r bit (addr:10h, d1-0) adc internal state 1111 x,xxx 0, 01 1, 01 power down initialize normal state power down 3088 / fs (1) (2) (6) alc state alc enable alc disable alc disable timer control (addr:1ah) xxh 0ah (3) alc control 1 (addr:1bh) xxh e1h (4) (7) (5) alc control 2 (addr:1ch) xxh 81h 01h (8) example: pll master mode audio i/f format:i2s sampling frequency:44.1khz pre mic amp:+15db mic power on alc setting:refer to figrure 37 alc bit = 1 (2) addr:12h, data:10h addr:13h, data:01h (3) addr:1ah, data:0ah (1) addr:15h, data:2fh (4) addr:1bh, data:e1h (6) addr:10h, data:07h recording (7) addr:10h, data:04h (5) addr:1ch, data:81h (8) addr:1ch, data:01h
[ ak570 1 ] ms0404 - j - 04 2015/10 - 58 - ??? adc ????????????? 1. pll ?`?? figure 53 . clock stopping sequence ( 1) < > (1) pll ?` : pmpll=m/s bits = 1 ? 0 (2) mcko ?? : mcko bit = 1 ? 0 (3) ??? 2. pll `?` (exlrck, exbclk p in) ? figure 54 . clock stopping sequence ( 2) < > (1) pll ?` : pmpll bit = 1 ? 0 (2) ??? * ` & ?`???? external mcki pmpll bit (addr:11h, d0) mcko bit (addr:16h, d2) input (3) (1) (2) "h" or "l" m/s bit (addr:11h, d1) example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz sampling frequency: 44.1khz (2) addr:16h, data:00h (1) addr:11h, data:10h (3) stop an external mcki exbclk pmpll bit (addr:11h, d0) input (1) (2) exlrck input (2) example : audio i/f format : i2s pll reference clock: exbclk bclk frequency: 64fs sampling frequency: 44.1khz (1) addr:11h, data:0ch (2) stop the external clocks
[ ak570 1 ] ms0404 - j - 04 2015/10 - 59 - 3. pll `?` (mcki pin) ? figure 55 . clock stopping sequence ( 3) < > (1) pll ?` : pmpll bit = 1 ? 0 (2) mcko ?? : mcko bit = 1 ? 0 (3) ??? 4. ??`?? ( `?` ) figure 5 6 . clock stopping sequence ( 4) < > (1) ??? * ?`???? 5. ??`?? ( ?` ) figure 57 . clock stopping se quence ( 5) < > (1) mcki ? bclk lrck h ? l ??? external mcki pmpll bit (addr:11h, d0) input (1) (3) mcko bit (addr:16h, d2) (2) example : audio i/f format: i2s pll reference clock: mcki=11.2896mhz exbclk frequency: 64fs sampling frequency: 44.1khz (1) addr:11h, data:10h (3) stop the external clocks (2) addr:16h, data:00h exlrck input (1) exbclk input (1) external mcki input (1) example : audio i/f format :i2s input mcki frequency:256fs sampling frequency:44.1khz (1) stop the external clocks lrck output bclk output external mcki input (1) "h" or "l" "h" or "l" example : audio i/f format :i2s input mcki frequency:256fs sampling frequency:44.1khz (1) stop mcki
[ ak570 1 ] ms0404 - j - 04 2015/10 - 60 - ?` ???`????? pmvcm bit = 0 ??M 20 ? a(typ) ? ???? (typ. 1 ? a) ? ??? pdn pin = l ? ?? ??
[ ak570 1 ] ms0404 - j - 04 2015/10 - 61 - ??` 24 - pin qfn (unit: mm) ? : ??`Y??? (exposed pad) ?`??????A |??? ??`| : ??? `??`| : ~ `??`I : ?oU?
[ ak570 1 ] ms0404 - j - 04 2015/10 - 62 - ?` ak5701vn xx x xx : date code identifier ( 5 ) ak5701kn xxxx x : date c ode identifier ( 5 ) 5701 xxxx x 1 5701k xxxx x [ 1
[ ak570 1 ] ms0404 - j - 04 2015/10 - 63 - ?s date (yy/mm/dd) revision reason page contents 05/08/04 00 `?? ? ? ? ? ? ?? ? ? ? ? ?`?` ?h ? ? ? ? ? u? ? ? ? ? ? ? ? ? ?? ? to cclk ? edge to cclk ? ? ? ? edge 2. control interface timing(csp pin = ? to cclk ? edge to cclk ? ? ? ? edge 3. note 22 ? `? ? ? ? ? ? ?? ???z? ? ?? ? ???z? ? ?? ? ? 12. ? ? ??`?` ??`??`??
[ ak570 1 ] ms0404 - j - 04 2015/10 - 64 - ?? 0. ?d?u??u????u???? ???u?????????? ?H???dQ????I?? s?I?_J 1. ?d??u??h?? ??H ?Z????b???^??g??SZ ??????CO?????????? ????????????????p ??????? 2. u???CC??C???C?C? CN??????C????g??? ]?b???p??? ?????O??m? ??????????o^??????e ?SZ????u????? ???u?????????p?? ????? 3. ?|m?????u??`???? ??u?????u?`????]? b??? ???????u?d??u ?????O??? 4. u???dg???_k??????? ?????????u???dg? ????????Q?m?? vB???A??u???dg ??t?u??????C? ??? ? 5. u??hm????????u?e???I??? u???H???|????? rohs ??m ?hvB?{??m????? ??????pv???? ?? 6. ??????????u??????p? ??????p??a ??? 7. ???????Z???d?}u?? ?

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